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Formal Semantics and Proof Techniques for Optimizing VHDL Models 4.0%OFF

Formal Semantics and Proof Techniques for Optimizing VHDL Models

by Kothanda Umamageswaran, Sheetanshu L. Pandey and Philip A. Wilsey

  • ISBN

    :  

    9780792383758

  • Publisher

    :  

    Springer

  • Subject

    :  

    Architecture, Computer Hardware, Technology, Engineering, Agriculture

  • Binding

    :  

    HARDCOVER

  • Pages

    :  

    184

  • Year

    :  

    1998

₹

13647.0

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₹

13101.0

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  • Description

    Written expressly for hardware designers, this book presents a formal model of VHDL clearly specifying both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL.

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