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VHDL Design Representation and Synthesis
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ISBN
:
9788131716076
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Publisher
:
Pearson
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Subject
:
Technology: General Issues
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Binding
:
Paperback
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Pages
:
668
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Year
:
2007
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499.0
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379.0
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Description
Intended to teach a synthesis-based approach to design using a hardware description language (i.e., VHDL), this text focuses on the synthesis process in how to translate VHDL descriptions into gate level logic.For Sale in Indian subcontinent onlyFeaturesThe comprehensive, up-to-date guide to synthesis-based design with VHDL. Includes an exceptionally clear introduction to structured design concepts and design tools. Master the ASIC design process and key implementation technologies: PLDs, FPGAs, gate arrays, and standard cells. ContentsStructured Design Concepts. Design Tools. Basic Features of VHDL. Lexical Description. Character Set. Basic VHDL Modeling Techniques. Algorithmic Level Design. Register Level Design. Gate Level and ASIC Library Modeling.HDL-Based Design Techniques. ASICs and the ASIC Design Proess. Modeling for Synthesis. Integration of VHDL into a Top-Down Design Methodology. Synthesis Algorithms for Design Automation.
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