Handbook of Digital Techniques for High-Speed Design : Design Examples, Signaling and Memory Technologies, Fiber Optics, Modeling, and Simulation to Ensure Signal Integrity

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This practical handbook fills in gaps that other textbooks on high-speed design don't discuss, covering every aspect of high-speed board-level digital design. Several design examples at high Gigabit per second data rates are presented. Discusses highest-speed logic and interface families of devices, relevant applications, and device speeds versus how far signals transmit with good signal integrity. A quick-reference overview of each device family is also provided. High-speed design rules are presented for both engineering design and printed circuit board layout. Emphasizes designing high-speed backplanes, driving cabling, bus architecture and topology. Discusses IBIS and SPICE modeling, simulations, design processes, and over 30 design automation tools. Quantifies signal integrity using jitter and bit error rate measurements, eye diagrams, time-domain reflectometry and transmission. Details high-speed transmission line and parasitic effects, cabling, connectors, single-ended/differential terminations, lab test equipment, and intellectual property. Dedicated chapter on fiber optics and when to use.For Sale in Indian subcontinent onlyFeaturesProvides detailed technical information on CML, SSTL, GTL/GTL+/GTLP, LVDS, Bus LVDS, M-LVDS, LVDM, ECL, PECL, LVPECL, HSTL, and more—plus applicationsbest suited for each Discusses IBIS and SPICE modeling and simulation, plus a full range of electronic design automation (EDA) tools Emphasizes backplane and bus design with detailed guidelines and design rules Covers fiber optics in detail—and when it makes sense to use them, and much more!ContentsPART I: INTRODUCTION. 1. Trends in High-Speed Design. 2. ASICs, Backplane Configurations, and SerDes Technology. 3. A Few Basics on Signal Integrity. PART II: SIGNALING TECHNOLOGIES AND DEVICES. 4. Gunning Transceiver Logic (GTL, GTLP, GTL+, AGTL+). 5. Low Voltage Differential Signaling (LVDS). 6. Bus LVDS (BLVDS), LVDS Multipoint (LVDM), and Multipoint LVDS (M-LVDS). 7. High-Speed Transceiver Logic (HSTL) and Stub-Series Terminated Logic (SSTL). 8. Emitter Coupled Logic (ECL, PECL, LVPECL, ECLinPS Lite and Plus, SiGe, ECL Pro, GigaPro and GigaComm). 9. Current-Mode Logic (CML). 10. FPGAs - 3.125 Gbps RocketIOs and HardCopy Devices. 11. Fiber-Optic Components. 12. High-Speed Interconnects and Cabling. PART III. HIGH-SPEED MEMORY AND MEMORY INTERFACES. 13. Memory Device Overview and Memory Signaling Technologies. 14. Double Data Rate SDRAM (DDR, DDR2) and SPICE Simulation. 15. GDDR3, ZBT, FCRAM, SigmaRAM, RLDRAM, DDR SRAM, Flash, FeRAM, and MRAM. 16. Quad Data Rate (QDR, QDRII) SRAM. 17. Direct Rambus DRAM (DRDRAM). 18. Xtreme Data Rate (XDR) DRAM, FlexPhase and ODR. PART IV: MODELING, SIMULATION, AND EDA TOOLS. 19. Differential and Mixed-Mode S.Parameters. 20. Time Domain Reflectometry (TDR), Time Domain Transmission (TDT), and VNAs. 21. Modeling with IBIS. 22. Mentor Graphics - EDA Tools for High-Speed Design, Simulation, Verification, and Layout. PART V: DESIGN CONCEPTS AND EXAMPLES. 23. Advances in Design, Modeling, Simulation, and Measurement Validation of High-Performance Board-to-Board 5-to-10 Gbps Interconnects. 24. IBIS Modeling and Simulation of High-Speed Fiber-Optic Transceivers. 25. Designing with LVDS. 26. Designing to 10 Gbps Using SerDes Transceivers, Serializers, and Deserializers. 27. WarpLink SerDes System Design Example. PART VI: EMERGING PROTOCOLS AND TECHNOLOGIES. 28. Electrical Optical Circuit Board (EOCB). 29. RapidIO. 30. PCI Express and ExpressCard. PART VII: LAB AND TEST INSTRUMENTATION. 31. Electrical and Optical Test Equipment.